(1) Field of the Invention
The invention relates to a method of fabricating semiconductor structures, and more particularly, to a method of forming polysilicon sidewall capacitors in the manufacture of an integrated circuit device.
(2) Description of the Prior Art
Capacitors are an important enabling component for integrated circuit manufacture. High unit capacitance structures are needed in the formation of memory cells such as SRAMs and DRAMs. Polysilicon-to-polysilicon parallel plate capacitors are a favored approach because neither plate comprises a substrate junction. Therefore, junction leakage and parasitic device concerns are avoided. Unfortunately, parallel plate structures often have a relatively low per unit area capacitance and therefore require large areas to form large capacitors.
Several prior art approaches concern the formation of sidewall capacitors and related structures. U.S. Pat. No. 5,498,889 to Hayden discloses a method to form sidewall capacitors on the sidewalls of via openings over MOS gates. A stack of dielectric-metal-dielectric is deposited over the MOS gate. A via opening is created over the gate through the stack. A metal sidewall spacer is formed in the via opening. A capacitor dielectric is then deposited. A second metal spacer is formed over the capacitor dielectric. The capacitor dielectric is etched through to expose the gate electrode. A metal layer is deposited to complete connectivity and the capacitor. U.S. Pat. No. 5,912,492 to Chang et al teaches a process to reduce hot carrier effects in a short channel MOSFET. After gate definition and lightly-doped drain (LDD) implantation, conductive sidewall spacers are formed on the gate. The conductive spacers overlie the gate oxide and the LDD and, thereby reduce the electric field and the hot carrier effect. U.S. Pat. No. 5,701,647 to Saenger et al discloses a method to form capacitors that eliminates contact between high dielectric constant material and silicon. Sidewall capacitors are formed by first patterning a stack of dielectric and conductive layers. Another conductive layer is then deposited. This conductive layer is anisotropically etched to form sidewalls. A capacitor dielectric layer is then deposited and etched down to overlie the conductive sidewalls. A metal layer is deposited to fill the trenches and to form the top plate for the capacitor. U.S. Pat. No. 5,760,435 to Pan teaches a method to form EEPROM cells with double floating gates. Conductive sidewalls are formed overlying tunnel oxide in the cell fabrication.